1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device. More specifically, the present invention relates to a method of fabricating a self-aligned gate pattern of a flash memory device.
2. Description of the Related Art
As the integration density of flash memory devices increases, the stacked gate patterns of the devices are becoming smaller. Recently, a self-aligned pattern formation process that includes chemical mechanical polishing (CMP) has been used to manufacture the stacked gate structures.
The self-aligned process will be described with reference to the flowchart of FIG. 1 and the cross-sectional views of FIGS. 2 through 9. FIGS. 2-9 show a substrate 10 divided into a cell area and a peripheral circuit area. A pad oxide layer 11, a floating gate 20, an inter-gate insulating layer 21, and a common source line 25 are formed in the cell area.
In step 1, a conductive layer 35, an anti-reflective layer 40, and an oxide layer 45 are sequentially formed on the entire surface of the substrate 10 (FIG. 2).
Next, a photolithography process is performed to leave the oxide layer 45 only in the peripheral circuit area. More specifically, in step 2, a photoresist pattern 50 for masking the peripheral circuit area is formed, and then the oxide layer 45 and the anti-reflective layer 40 in the cell area are removed, as shown in FIG. 3.
In step 3, a nitride layer 60 serving as an oxidation blocking layer is formed on the entire surface of the substrate 10 to a thickness of about 1500 xc3x85 (FIG. 4). Next, in step 4, the portion of the surface of the conductive layer 35 above the floating gate 20 and the common source line 25 is exposed by CMP, as shown in FIG. 5.
An oxidation process is then performed in step 5. As a result, as shown in FIG. 6, an oxide layer 70 is formed only on the exposed portion of the conductive layer 35, i.e., is not grown on the portion covered by the nitride layer 60. The oxide layer 70 forms a hard mask, for use in forming a control gate, when the nitride layer 60 is removed (step 6 as shown in FIG. 7). In other words, the hard mask 70 is formed by self-aligned CMP and an oxidation process.
Hard masks 85 are then formed in the peripheral circuit area (step 7). In particular, the entire surface of the substrate 10 is coated with a photoresist. Next, photoresist patterns 80 defining gate patterns are formed in the peripheral circuit area by an exposure and development process. The hard masks 85 are formed by etching the oxide layer 45 and the anti-reflective layer 40 remaining in the peripheral circuit area using the photoresist patterns 80 as an etch mask, as shown in FIG. 8.
The photoresist patterns 80 are then removed. Next, the conductive layer 35 formed in step 1 is etched using the hard mask 70 in the cell area and the hard masks 85 in the peripheral circuit area as an etch mask, to form a control gate 90 in the cell area and gates 95 in the peripheral circuit area (step 8, as shown in FIG. 9). Accordingly, a stacked gate structure is formed in the cell area.
In the prior art described above, forming the control gate by a self-aligned method makes it is easy to then form a very small stacked gate structure. However, the CMP process used in this method presents several problems. In the case where the nitride layer 60, i.e., the oxidation-blocking layer, is chemically mechanically polished, the conductive layer 35 can be over-etched. When this occurs, the resistance of the gates increases. Also, CMP requires complicated apparatus including a slurry spraying system, CMP polishing mechanisms, a CMP stopping point detecting apparatus, a waste chemical material removing system, and a cleaning apparatus. Still further, a large amount of chemicals (slurry), a pad, and other items are used up and hence, must be replenished, in CMP. Accordingly, CMP is a costly process to implement and perform. Also, a photolithography process for exposing the cell area must be performed before CMP, thereby complicating the process of fabricating the flash memory device.
An object of the present invention is to solve the above-described problems and limitations inherent in the prior art. More specifically, it is an object of the present invention to provide a method of fabricating a highly integrated flash memory device that is relatively easy to execute using a simple manufacturing system.
The method of fabricating a flash memory device according to the present invention comprises a self-aligned non-exposure pattern formation process. A conductive layer and an oxidation-blocking layer are formed on a stepped pattern including a floating gate pattern and an inter-gate insulating layer pattern such that the conductive layer and the oxidation-blocking layer conform to the stepped pattern. A photoresist layer is formed on the oxidation-blocking layer, whereby the photoresist layer has an upper surface situated above the oxidation-blocking layer. A portion of the photoresist layer is dissolved by soaking the photoresist layer in developing solution. The upper surface of the photoresist layer is brought below the upper surface of that part of the oxidation-blocking layer on the stepped pattern, without having photo exposed the photoresist layer. The resulting photoresist pattern exposes part of the oxidation-blocking layer. A blocking layer pattern exposing the conductive layer is formed on the stepped pattern by removing the exposed part of the oxidation-blocking layer. The photoresist pattern is then removed. A hard mask defining a control gate is formed by oxidizing the surface of the conductive layer exposed by the blocking layer pattern. The blocking layer pattern is then removed. A control gate is formed by etching the conductive layer using the hard mask as an etch mask. A stacked gate structure is formed once the hard mask is removed.
Preferably, the photoresist layer is removed by soaking the layer in a developing solution until the height or thickness of the photoresist layer is equal to or less than 10% of that of the portion of the conductive layer disposed over the stepped pattern, and then etching back the photoresist layer remaining on the stepped pattern. The height of the photoresist pattern is 20-90% of the height of the conductive layer on the stepped pattern.
A nitride layer is formed to a thickness of 50-100 xc3x85 or an oxynitride layer is formed to a thickness of 50-600 xc3x85 to form the oxidation blocking layer.
The photoresist layer is preferably formed of photoresist including a first novolak resin and a photoactive compound of 3-15 wt % based on the total weight of the first novolak resin, or of photoresist including a first novolak resin, a second novolak resin of 10-60 wt % based on the total weight of the first novolak resin and having a rate of dissolution in the developing solution of 300-1500 xc3x85/sec, and a photoactive compound of 15-30 wt % based on the total weight of the first novolak resin, or of photoresist including a first novolak resin, polyhydroxystyrene of 10-60 wt % based on the total weight of the first novolak resin, and a photoactive compound of 15-30 wt % based on the total weight of the first novolak resin.
The photoresist layer may also be formed of photoresist including a polymer, in which a t-butyloxycarbonyl group and an acetal group are combined with a backbone of the polymer as a protecting group, and a photoacid generator of 0.5-8 wt % based on the total weight of the polymer. In this case, the photoresist layer is preferably baked before being soaked in the developing solution. The baking may be performed in a single stage at 130-160xc2x0 C. for 30-120 seconds or in a first baking stage at 90-120xc2x0 C. for 30-120 seconds followed by a second stage at 130-160xc2x0 C. for 30-120 seconds.